General description
1.1Overview
The A700x family is a tamper resistant secure Micro Controller Unit (MCU) family using a dedicated security hardened MX51CPU. NXP Semiconductors has a long track record in security MCUs. NXP ICs have been used in all types of security applications such as bank cards, health insurance cards, electronic passports, and pay-TV cards. They have also been used as embedded secure element in mobile phones. The A700x family features a significantly enhanced secure microcontroller architecture. Extended instructions for Java and C code, linear addressing and high speed at low power are among many other improvements added to the classic 80C51 core architecture.
The A700x family supports the following features:
•Dedicated MX51 security CPU
•100 kbit/s I2C slave interface
•ISO/IEC 7816 interface (optional)
•ISO/IEC14443 interface (optional)
•40 C to +90 C operational ambient temperature (optional)
•On-chip operating system firmware: JCOP 2.4.2
•X.509 certificate-based client authentication application pre-installed
•Secure generation and insertion of key and certificate data, individualized
for each die (optional)
•NXP glue logic
•NXP secure fetch technology
•Active shielding technology
•Asynchronous self-timed Handshake Technology
•Up to 76 kB EEPROM for application-code and data
•40 A typical sleep mode current with I2C pads operated in weak pull-up mode, do not obstruct the bus lines
•High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA up to 2048-bit keys, ECC over GF(p) up to 320-bit keys)
•Secured 2-key/3-key triple-DES coprocessor
•Secured AES coprocessor (128-, 192- and 256-bit keys)
•Compliant to Java Card specification V3.0.1 classic as defined in Ref. 1
•Compliant to Global Platform specification as defined in Ref. 2 and Ref. 3
Features and benefits
2.1Standard family features
High reliable EEPROM for both data storage and program execution: 80 kB
Data retention time: 25 years minimum
Endurance: 500,000 cycles minimum
Dedicated Secure_MX51 MCU (Memory eXtended/enhanced 80C51)
100 kbit/s I2C slave interface
Optional ISO/IEC 7816 contact interface
Optional ISO/IEC 14443 A Contactless Interface Unit (CIU)
Public Key Cryptography (PKC) coprocessor supporting RSA, Elgamal, DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
RSA support for the key lengths up to 2048 bit
Elliptic Curve over GF(p) Cryptography with key lengths up to 320 bit
Single DES (56 bit) and Triple DES with 2 or 3 Keys (112 bit or 168 bit), encryption and decryption in ECB, CBC and CBC-MAC mode
High-speed AES coprocessor (128-bit parallel processing AES engine)
Low-power True Random Number Generator (TRNG) in hardware, AIS-31 compliant
SHA1, SHA-224 and SHA-256
SEED algorithm
MD5
On-Chip Key generation
CRC calculations
Data Authentication Pattern (DAP) for the Supplementary Security Domains
Low power and low voltage design using NXP Semiconductors handshaking technology
Power-saving SLEEP mode
Wake-up from SLEEP mode by any I2C communication request
40 A typical sleep mode current with I2C pads operated in weak pull-up mode, do not obstruct the bus lines
Internally generated CPU clock (typical 62 MHz)
1.62 V to 5.5 V operating voltage range