• Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
• <0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz
• Operating modes: locked to input signal, holdover and free-run
• Initial holdover accuracy of ±50ppb
• Accepts up to two LVPECL, LVDS, LVHSTL, HCSL, or LVCMOS
input clocks
• Accepts frequencies ranging from 8kHz up to 875MHz
• Auto and manual input clock selection with hitless switching
• Clock input monitoring, including support for gapped clocks
• Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
• Operates from a 10MHz to 40MHz fundamental-mode crystal
• Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output clocks
• Output frequencies ranging from 8kHz up to 1.0GHz (diff)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Four General Purpose I/O pins with optional support for status &
control:
• Four Output Enable control inputs may be mapped to any of the
eight outputs
• Lock, Holdover and Loss-of-Signal status outputs
• Open-drain Interrupt pin
• Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz
• Optional Fast Lock function
• Programmable output phase delays in steps as small as 16ps
• Register programmable through I2C or via external I2C EEPROM
• Bypass clock paths for system tests