1 Features
• Output frequency: 300MHz to 12.8GHz
• Noiseless adjustable input delay up to 60ps with
1.1ps resolution
• Individual adjustable output delays up to 55ps with
0.9ps resolution
• Ultra-low noise
– Noise floor: –159dBc/Hz at 6GHz output
– Additive jitter (DC to fCLK): 36fs
– Additive jitter (100Hz to 100MHz): 10fs
• Four high-frequency clocks with corresponding
SYSREF outputs
– Shared divide by 1 (Bypass), 2, 3, 4, 5, 6, 7,
and 8
– Shared programmable multiplier x2, x3, x4, x5,
x6, x7 and x8
• LOGICLK output with corresponding SYSREF
output
– On separate divide bank
– 1, 2, 4 pre-divider
– 1 (bypass), 2, …, 1023 post divider
– Second logic clock option with additional divider
1, 2, 4 & 8
• Six programmable output power levels
• Synchronized SYSREF clock outputs
– 508 delay step adjustments of less than 2.5ps
at 12.8GHz
– Generator, repeater and repeater retime modes
– Windowing feature for SYSREFREQ pins to
optimize timing
• SYNC feature to all divides and multiple devices
• Operating voltage: 2.5V
• Operating temperature: –40ºC to +85ºC

2 Applications
• Test & Measurement:
– Oscilloscope
– Wireless equipment testers
– Wideband digitizers
• Aerospace & Defense:
– Radar
– Electronic warfare
– Seeker Front end
– Munitions
– Phase array antenna / Beam forming
• General Purpose:
– Data converter clocking
– Clock buffer distribution / division

3 Description
The high frequency capability, extremely low jitter
and programmable clock input and output delay
of this device, makes a great approach to clock
high precision, high-frequency data converters without
degradation of signal-to-noise ratio. Each of the four
high frequency clock outputs and additional LOGICLK
outputs with larger divider range, is paired with a
SYSREF output clock signal. The SYSREF signal
for JESD204B/C interfaces can either be internally
generated or passed in as an input and re-clocked
to the device clocks. The noiseless delay adjustment
at input path of the high frequency clock input
and individual clock output paths insures low skew
clocks in multi-channel system. For data converter
clocking application, having the jitter of the clock
less than the aperture jitter of the data converter
is important. In applications where more than four
data converters need to be clocked, a variety of
cascading architectures can be developed using
multiple devices to distribute all the high frequency
clocks and SYSREF signals required. This device,
combined with an ultra-low noise reference clock
source, is an exemplary choice for clocking data
converters, especially when sampling above 3GHz.