1 Features
• Fully configurable dual-rail design allows each port
to operate with a power supply range from 0.65V
to 3.6V
• Operating temperature from –40°C to +125°C
• Multiple direction control pins to allow
simultaneous up and down translation
• Glitch-free power supply sequencing
• Up to 380Mbps support when translating from 1.8V
to 3.3V
• VCC isolation feature:
– If either VCC input is below 100mV, all
I/Os outputs are disabled and become highimpedance
• Ioff supports Partial-Power-Down mode operation
• Compatible with AVC family level shifters
• Latch-up performance exceeds 100mA per JESD
78, Class II
• ESD protection exceeds JESD 22:
– 8000V Human-Body Model
– 1000V Charged-Device Model

2 Applications
• Enterprise and communications
• Industrial
• Personal electronics
• Wireless infrastructure
• Building automation
• Point of sale

3 Description
The SN74AXC4T245 is a four-bit noninverting bus
transceiver that uses two individually configurable
power-supply rails. The device is operational with both
VCCA and VCCB supplies as low as 0.65V. The A port
is designed to track VCCA, which accepts any supply
voltage from 0.65V to 3.6V. The B port is designed
to track VCCB, which also accepts any supply voltage
from 0.65V to 3.6V. Additionally the SN74AXC4T245
is compatible with a single-supply system.
The SN74AXC4T245 device is designed for
asynchronous communication between data buses.
The device transmits data from the A bus to the B bus
or from the B bus to the A bus, depending on the logic
level of the direction-control inputs (1DIR and 2DIR).
The output-enable inputs (1 OE and 2 OE) are used
to disable the outputs so the buses are effectively
isolated. The SN74AXC4T245 device is designed so
the control pins (xDIR and x OE) are referenced to
VCCA.
To put the level shifter I/Os in the high-impedance
state during power up or power down, tie the xOE
pins to VCCA through a pullup resistor.
This device is fully specified for partial-power-down
applications using the Ioff current. The Ioff protection
circuitry ensures that no excessive current is drawn
from or to an input, output, or combined I/O that
is biased to a specific voltage while the device is
powered down.
The design of the VCC isolation feature allows both
I/O ports to enter a high-impedance state by disabling
their outputs if either VCCA or VCCB is less than
100mV.
Glitch-Free power supply sequencing allows either
supply rail to be powered on or off in any order while
providing robust power sequencing performance.