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SN74LVCZ161284A Datasheet (PDF) - Texas Instruments

SN74LVCZ161284A Datasheet PDF - Texas Instruments
Part # SN74LVCZ161284A
Download  SN74LVCZ161284A Download
File Size   927.85 Kbytes
Page   16 Pages
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments
Description 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

SN74LVCZ161284A Datasheet (PDF)

Go To PDF Page Download Datasheet
SN74LVCZ161284A Datasheet PDF - Texas Instruments

Part # SN74LVCZ161284A
Download  SN74LVCZ161284A Click to download

File Size   927.85 Kbytes
Page   16 Pages
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments
Description 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

SN74LVCZ161284A Datasheet (HTML) - Texas Instruments


SN74LVCZ161284A Product details

FEATURES
· Power-On Reset (POR) Prevents Printer
Errors When Printer Is Turned On, But No
Valid Signal Is at Pins A9–A13
· Operates From 3 V to 3.6 V
· 1.4-kW Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
· Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type) Electrical
Specifications
· Flow-Through Architecture Optimizes PCB
Layout
· Ioff and Power-Up 3-State Support Hot
Insertion
· Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
· ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 350-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION
The SN74LVCZ161284A is designed for 3-V to 3.6-V
VCC operation. This device provides asynchronous
two-way communication between data buses. The
control-function implementation minimizes external
timing requirements.
is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and
four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to
drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a
totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements
as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface
specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have
a 1.4-kW integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low
state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.




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