1 Features
1• 5962R0626201VXC
– Total Ionizing Dose (TID) 100 krad(Si)
– Single Event Latch-up 120 MeV-cm2/mg
(See Radiation Reports)
• 1.1-GHz Full-Power Bandwidth
• Internal Sample-and-Hold Circuit
• Low-Power Consumption
• Internal Precision 1-V Reference
• Single-Ended or Differential Clock Modes
• Data Ready Output Clock
• Clock Duty Cycle Stabilizer
• Dual 3.3-V and 1.8-V Supply Operation (±10%)
• Power-Down Mode
• Offset Binary or 2's Complement Output Data
Format
• 48-pin CFP Package (11.5-mm × 11.5-mm, 0.635-
mm Pin-Pitch)
• Key Specifications
– Resolution 14 Bits
– Conversion Rate 155 MSPS
– SNR (fIN = 70 MHz) 70.1 dBFS (typ)
– SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
– ENOB (fIN = 70 MHz) 11.3 Bits (typ)
– Full-Power Bandwidth 1.1 GHz (typ)
– Power Consumption 967 mW (typ)

2 Applications
• High IF Sampling Receivers
• Power Amplifier Linearization
• Multi-Carrier, Multi-Mode Receivers
• Test and Measurement Equipment
• Communications Instrumentation
• Radar Systems

3 Description
The ADC14155QML-SP is a high-performance
CMOS analog-to-digital converter capable of
converting analog input signals into 14-bit digital
words at rates up to 155 MSPS. This converter uses
a differential, pipelined architecture with digital error
correction and an on-chip sample-and-hold circuit to
minimize power consumption and the external
component count, while providing excellent dynamic
performance. A unique sample-and-hold stage yields
a full-power bandwidth of 1.1 GHz. The ADC14155
operates from dual 3.3-V and 1.8-V power supplies
and consumes 967 mW of power at 155 MSPS.
The separate 1.8-V supply for the digital output
interface allows lower power operation with reduced
noise. A power-down feature reduces the power
consumption to 5 mW with the clock input disabled,
while still allowing fast wake-up time to full operation.
The differential inputs provide a full scale differential
input swing equal to 2 times the reference voltage. A
stable 1-V internal voltage reference is provided, or
the ADC14155 can be operated with an external
reference. The Clock mode (differential versus singleended)
and output data format (offset binary versus
2's complement) are pin-selectable. A duty cycle
stabilizer maintains performance over a wide range of
clock duty cycles.
The ADC14155QML-SP is available in a 48-lead
thermally enhanced multi-layer ceramic quad
package and operates over the military temperature
range of –55°C to +125°C.