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LF398 Datasheet (PDF) - SYC Electronica

LF398 Datasheet PDF - SYC Electronica
Part # LF398
Download  LF398 Download
File Size   546.15 Kbytes
Page   13 Pages
Manufacturer  SYC [SYC Electronica]
Direct Link  https://www.sycelectronica.com.ar/index.php
Logo SYC - SYC Electronica
Description Monolithic Sample-and-Hold Circuits

LF398 Datasheet (PDF)

Go To PDF Page Download Datasheet
LF398 Datasheet PDF - SYC Electronica

Part # LF398
Download  LF398 Click to download

File Size   546.15 Kbytes
Page   13 Pages
Manufacturer  SYC [SYC Electronica]
Direct Link  https://www.sycelectronica.com.ar/index.php
Logo SYC - SYC Electronica
Description Monolithic Sample-and-Hold Circuits

LF398 Datasheet (HTML) - SYC Electronica


LF398 Product details

Features
n Operates from ±5V to ±18V supplies
n Less than 10 μs acquisition time
n TTL, PMOS, CMOS compatible logic input
n 0.5 mV typical hold step at Ch = 0.01 μF
n Low input offset
n 0.002% gain accuracy
n Low output noise in hold mode
n Input characteristics do not change during hold mode
n High supply rejection ratio in sample or hold
n Wide bandwidth
n Space qualified, JM38510

General Description
The LF198/LF298/LF398 are monolithic sample-and-hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 μs to
0.01%. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accomplished
with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF198 to be included inside
the feedback loop of 1 MHz op amps without having stability
problems. Input impedance of 1010W allows high
source impedances to be used without degrading accuracy.
P-channel junction FET’s are combined with bipolar devices
in the output amplifier to give droop rates as low as 5 mV/min
with a 1 μF hold capacitor. The JFET’s have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.




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