DESCRIPTION
The PM7385 FREEDM-84A672 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing for a maximum of 672 bi-directional channels.

FEATURES
• Single-chip multi-channel HDLC controller with a 50 MHz, 16 bit “Any-PHY” Packet Interface (APPI) for transfer of packet data using an external controller.
• Supports up to 672 bi-directional HDLC channels assigned to a maximum of 84 channelised or unchannelised links conveyed via a Scaleable Bandwidth Interconnect (SBI) interface.
• Data on the SBI interface is divided into 3 Synchronous Payload Envelopes (SPEs). Each SPE can be configured independently to carry data for either 28 T1/J1 links, 21 E1 links, or 1 unchannelised DS-3 link.
• Links in an SPE can be configured individually to operate in clear channel mode, in which case, all framing bit locations are assumed to be carrying HDLC data.
• Links in an SPE can be configured individually to operate in channelised mode, in which case, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1 links) and from 1 to 31 (for E1 links).
• Supports three bi-directional HDLC channels each assigned to an unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz. Each link may be configured individually to replace oneof the SPEs conveyed on the SBI interface.
• For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences.
• For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value.
• Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently on the receive APPI. For channelised links, the octets are aligned with the receive time-slots.
• For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
• For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the external controller or automatically when the channel underflows.
• Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from the transmit APPI. For channelised links, the octets are aligned with the transmit time-slots. • Supports per-channel configurable APPI burst sizes of up to 256 bytes for transfers of packet data.
• The FREEDM maintains packet level performance metrics such as number of received packets, number of received packets with frame check sequence errors, number of transmitted packets, number of receive aborted packets, and number of transmit aborted packets.
• Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and the receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering.
• Provides a 16 bit microprocessor interface for configuration and status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
• Supports 3.3 Volt tolerant I/O.
• Low power 2.5 Volt 0.25 μm CMOS technology.
• 352 pin enhanced ball grid array (SBGA) package.

APPLICATIONS
• IETF PPP interfaces for routers
• Frame Relay interfaces for ATM or Frame Relay switches and multiplexors
• FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors.
• Internet/Intranet access equipment.
• Packet-based DSLAM equipment.
• Packet over SONET.
• PPP over SONET.