1 General description
This document describes the functionality and electrical specification of the PN7220 high-power NFC controller family with NCI interface. As an NCI 2.2 compliant NFC controller with high RF output (2 W) and high receiver sensitivity, the NXP PN7220 is a robust solution for payment terminals and all readers that must generate a strong RF field in a difficult environment. Offering full compliance with EMVCo 3.1 L1 analog and digital, the PN7220 simplifies designs while ensuring interoperability with a broad range of smartcards and mobile phones. In addition to the reader/writer functionality, the device supports the host card emulation of ISO14443-A cards up to 848 kbit/s and allows to connect up to 3 TDA8035 which offer the possibility for an ISO7816 contact interface connection. The PN7221 is based on the PN7220 and supports all features of PN7220 plus "Enhanced Contactless Polling" (ECP) by Apple - this description is not part of this document. Note, that the ECP feature is available after formal authorization only.
Two host connection options are available for this product:
1. Connection to one single host - this is typically one host running an Android operating system
2. Connection to two hosts - in this case one host is typically a security CPU connected by the SPI interface to meet PCI compliance requirements for an EMVCo payment subsystem, and the second host connected by an I2C interface which is typicallly used to run an Android operating system for all non-EMVCo payment related applications. The PN7220 communicates with a connected host through a physical interface using the NCI 2.2 protocol. The PN7220 supports two types of configurable polling loops: one NFC Forum polling loop, and one EMVCo compliant polling loop. Switching between the polling loops is done based on a hardware input (GPIO) triggered by a connected host - in case of a switching of the polling loop all data from an ongoing transaction is cleared from the internal buffers, the NCI software stack is beeing reset and an RF reset is beeing executed. This helps to ensure data integrity for the performed transaction and allows to connect the right logical software endpoints to each of the polling loops. To speed-up the switching between NFC Forum polling and EMVCo polling and ease the RF configuration of each polling loop, two independent sets of RF configuration data can be stored in EEPROM. This allows to optimize each polling loop to meet individual RF requirements.
The PN7220 product family supports highly innovative and unique features which do not require any host controller interaction. These features include dynamic power control (DPC), adaptive waveform control (AWC), and fully automatic EMD error handling.
Additional documents supporting a design-in of the are available from NXP, this additional design-in information is not part of this document. In this document, the term "MIFARE card" refers to a contactless card with an embedded MIFARE IC.

2 Features and benefits
2.1 RF functionality
2.1.1 ISO/IEC14443-A
• Reader/writer mode supporting ISO/IEC 14443-A R/W up to 848 kbit/s
2.1.2 ISO/IEC 14443-B
• Reader/writer mode supporting ISO/IEC 14443-B up to 848 kbit/s
2.1.3 FeliCa
• Reader/writer mode supporting FeliCa 212 kbit/s and 424 kbit/s (without crypto)
2.1.4 Tag type reading
• Supports reading of all NFC tag types ( type 2, type 3, type 4A and type 4B, type 5 )
2.1.5 MIFARE card reading
• Reader/writer communication mode for the MIFARE card family including MIFARE Classic
Crypto supporting MIFARE Classic en-/decryption is integrated in hardware
2.1.6 ISO/IEC 15693
• Reader/writer mode supporting ISO/IEC 15693 (ICODE)
– RX: "Manchester" encoding with 424 kHz single-subcarrier (SSC) and 6.6 kBd
– RX: "Manchester" encoding with 424 kHz single-subcarrier (SSC) and 26 kBd
– RX: "Manchester" encoding with 424 kHz single-subcarrier (SSC) and 53 kBd
– TX: "1 of 4" encoding with 10 % modulation (53 kBd)
– TX: "1 of 4" encoding with 100 % modulation (53 kBd).
2.1.7 NFC Forum compliancy
• NFC Forum version 13 compliance for R/W – analog and digital
2.1.8 EMVCo contactless compliancy
• Contactless EMVCo 3.1 compliance for R/W – digital
• Contactless EMVCo 3.1 compliance for R/W analog can be achieved, but depends on connected antenna
geometry and size, matching network and RF settings.
2.1.9 Host interface
The devices PN7220 and PN7221 support one host interface using a single interface connection based on a I2C
interface host interface (host interface 1) with data rates up to 3.4 Mbit/s.
In addition, the device support two host interfaces using one interface connection based on a I2C interface (host
interface 2) up to 3.4Mbit/s and one SPI interface (host interface 1) up to 15Mbit/s.
The logical interface layer of the host interfaces is based on the NCI 2.2 interface specification, enhanced by
NXP proprietary commands.
2.2 Transmitter
• Transmitter with high RF output power of 2.0 W
• Dynamic power control 2.0 (DPC) (dynamic power control without processing load on host MCU)
• Adaptive waveshaping control (AWC)
2.3 Receiver
• Robust receiver: Automatic configuration, advanced insensitivity against TFT display noise for higher RF
performance
2.4 Integrated polling loop
• RF polling loop according to NFC Forum
• RF Polling loop according to EMVCo 3.1, integrated EMVCo L1 software stack
2.5 Integrated DC-DC
The PN7220 implements an integrated DC-DC which can be used to supply the transmitter. Since the supply
voltage of the transmitter LDO can be up to 6.0 Volts, this simplifies the design of the power supply.
A single supply concept for the RF system, for example, with single 3.3 V supply, is possible and allows making
use of the maximum RF output power by providing a maximum transmitter supply voltage.
The integrated DC-DC is used by the dynamic power control (DPC) to reduce the maximum power dissipation
of the chip.
The usage of the DC-DC is optional.
For applications making use of the low-power card detection, the DC-DC is available.
2.6 RF debugging support
• RF debugging without external probing of test signals possible by sampling debug data into chip-internal
memory based on pre-define trigger conditions – ideal debugging solution for PCI-compliant POS terminals
• One digital and one analog debug signal is provided by the chip for connection of an oscilloscope
2.7 ISO7816 contact interface
The product supports the connection of up to three TDA8035 ICs which is the default EEPROM configuration of the device.
The device features an integrated EMVCo L1 contact card activation, and is compliant with contactless EMVCO specification 3.x. The contact interface can be used for a single or dual host configuration.

3 Applications
• Payment terminals following the COTS security requirements with full EMVCo3.1 analog and digital
compliancy
• Multi-Application terminals
• Ticket validators for the controlling staff in public transport
• E-Vehicle charging stations
• Vending machines