FEATURES
• CMOS level input
• 384 Outputs
• Input of 6 bits (gradation data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and
a D/A converter
• Logic power supply voltage (VDD1) : 3.3 V V
• Driver power supply voltage (VDD2) : 8.5 V V
• High-speed data transfer : fCLK = 45 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)
• Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output Voltage polarity inversion function (POL)
• Display data inversion function (POL2)
• Single bank arrangement is possible (Loaded with slim or bending TCP)
+0.3
–0.6
+0.5
–1.0