■ Arm® Cortex®-M33 Core
● Armv8-M architecture with the main extension
● Maximum operating frequency: 200 MHz
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by LOCO or system clock
● CoreSight™ ETM-M33
■ Memory
● Up to 2-MB code flash memory
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
● 512-KB SRAM
■ Connectivity
● Serial Communications Interface (SCI) × 10
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Smart card interface
– Simple IIC
– Simple SPI
– Manchester coding (SCI3, SCI4)
● I2C bus interface (IIC) × 3
● Serial Peripheral Interface (SPI) × 2
● Quad Serial Peripheral Interface (QSPI)
● Octa Serial Peripheral Interface (OSPI)
● USB 2.0 Full-Speed Module (USBFS)
● USB 2.0 High-Speed Module (USBHS)
● CAN with Flexible Data-rate (CANFD) × 2
● Ethernet MAC/DMA Controller (ETHERC/EDMAC)
● SD/MMC Host Interface (SDHI)
● Serial Sound Interface Enhanced (SSIE)
● Consumer Electronics Control (CEC)
■ Analog
● 12-bit A/D Converter (ADC12) × 2
- 5 Msps at interleaving
● 12-bit D/A Converter (DAC12) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 6
● Low Power Asynchronous General Purpose Timer (AGT) × 6
■ Security and Encryption
● Secure Crypto Engine 9
– Symmetric algorithms: AES
– Asymmetric algorithms: RSA, ECC, and DSA
– Hash-value generation: SHA224, SHA256, GHASH
– 128-bit unique ID
● Arm® TrustZone®
– Up to three or six regions for the code flash, depending on the
bank mode
– Up to two regions for the data flash
– Up to three regions for the SRAM
– Individual secure or non-secure security attribution for each
peripheral
● Device lifecyle management
● Pin function
– Up to three tamper pins
– Secure pin multiplexing
■ System and Power Management
● Low power modes
● Battery backup function (VBATT)